Existing computer systems conventionally transfer data between devices, such as a memory controller and a memory device, in accordance with periodic signals and a predefined clocking scheme. Clock signals may be used to establish the timing of a transmitted signal or the timing at which an operation is performed on the signal. For example, data may be transferred to and from devices, such as a double-data rate synchronous dynamic random access memory (DDR SDRAM) device, in a source synchronous manner (i.e., the transmitting and receiving devices operate synchronously, in order to increase the speed of data transmission). In a source synchronous scheme, one or more strobe (clock) signals are transmitted along with a data signal along a transmission path. At a receiving device, the data signals are latched with reference to the strobe signal.
In a conventional DDR SDRAM, a data driver receives an internal data signal and outputs the data signal in response to being clocked by an internal clock signal. Ideally, the data driver outputs the data signal on an electrical interconnect in synchronism with a data strobe signal generated by a strobe driver. As required by a specific application, data drivers and strobe drivers may be programmed to operate in one of many drive strength modes (e.g., half, quarter, and one-eighth drive strength). A memory controller typically sets the output drive strength through the extended load mode register via a load mode register command to thereby place the data drivers and strobe drivers in the desired operating mode.
As shown in FIG. 1, a conventional memory system 100 may include a memory 102 and a memory controller 104. Memory 102 may include a plurality of data drivers 110 configured to transmit and receive data across a data bus 112. Furthermore, memory 102 may include one or more strobe drivers 114 configured to transmit and receive strobe signals across a strobe transmission line 108. Memory controller 104 may also transmit a plurality of commands over control bus 116. For example, control bus 116 may transmit a load mode register command including a desired drive strength to be programmed to drivers within memory 102. Extended mode register 120 may then set the drive strength accordingly for all data drivers 110 and strobe drivers 114 within memory 102. As shown in FIG. 1, conventional memories include one set of configured bits for setting data drivers 110 and strobe drivers 114.
As known in the art, an incoming strobe signal should transition through a threshold region in a smooth, linear manner. If a strobe signal changes direction within the threshold region or ledges (i.e., flat lines), a receiving circuit within a receiving device may register multiple data bits within a single clock period which may invalidate the data sequence or cause a system failure. Furthermore, as known in the art, the transition of data signals through the threshold region is inconsequential so long as setup and hold requirements are met (i.e., data signals must remain out of the threshold region as a strobe signal transitions through the threshold region).
For example, FIG. 2 illustrates a plot of a signal 103 driven by a driver operating in a half-strength mode. As known in the art, signal 103 may be a strobe signal or a data signal. If signal 103 is representative of a strobe signal, non-monotonic behavior requirements are violated (i.e., it does not transition through threshold region 105 in a smooth, linear fashion) at point 106. Conversely, if signal 103 is a data signal, and so long as setup and hold requirements are met, signal 103 may be a valid data signal.
Conventionally, data and strobe driver strengths are applied uniformly to all data and strobe drivers within a single memory device and, therefore, all data and strobe drivers operate at the same drive strength. However, strobe signals may experience problems when generated by drivers operating at lower drive strengths and, thus, strobe drivers operating at stronger drive strengths may be desirable. On the other hand, data signals may still meet all timing and signal quality requirements while being driven by drivers operating at lower drive strengths.
In view of the differing signal strength requirements for strobe and data drivers, methods, systems, and apparatuses having a capability for separately programmable data drivers and strobe drivers within a device, such as a memory device would be desirable. Specifically, it would be desirable to implement a device operable with data drivers and strobe drivers that may be programmed to operate at independent drive strengths.